Cost Measures in VLSI Array Design∗

نویسندگان

  • Peter Cappello
  • Sanjay Rajopadhye
چکیده

Using a directed acyclic graph (dag) model of algorithms, several computational complexity measures are defined in terms of time, period, and processors. Research interest is explained for designs that are timeminimal, processor-time-minimal, and period-processortime-minimal. Such designs are illustrated with the standard matrix product algorithm, modeled by the n×n×n directed mesh.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. &#10The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...

متن کامل

Design and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...

متن کامل

Advances in VLSI Design and Product Development Challenges

Low product life cycle, high non-recurring expenses and increasing development costs is forcing product makers to design more and more complex chips. Today's product market demands hardware with high performance, higher functionality, smaller form factor and lower power consution. This has led to adoption of rapidly changing technologies such as systems-on-chip with multiple core architectures,...

متن کامل

A New Vlsi Architecture for 2-d Dst Transform of Prime Length

Using a recently proposed VLSI algorithm for 2-D discrete sine transform (DST) an efficient VLSI architecture is proposed. This VLSI architecture has a modular and regular hardware structure and can compute in parallel thus resulting in high speed performances. The proposed architecture has been obtained by mapping the VLSI algorithm into two linear systolic arrays and combining them into a sin...

متن کامل

Design Investigation of Microstrip Patch and Half-Mode Substrate Integrated Waveguide Cavity Hybrid Antenna Arrays

In this paper two linear arrays including a linear 1×4 and a planar 2×2 of microstrip patch and half-mode substrate integrated waveguide (SIW) cavity hybrid antenna are introduced and investigated. These are simply implemented using low cost single layer printed circuit board (PCB) process. The array element consists of a rectangular microstrip patch with appropriate dimensions in the vicinity ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2008